Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Fiche De Données
Codes de produits
AT32UC3A3-XPLD
235
32072H–AVR32–10/2012
AT32UC3A3
16.8.3
Configuration Register
Register Name:
CR
Access Type:
Read/Write
Offset:
0x08
Reset Value:
0x852372C0
• TXSR: Exit Self Refresh to Active Delay
Reset value is eight cycles.
This field defines the delay between SCKE set high and an Activate command in number of cycles. Number of cycles is between
0 and 15.
• TRAS: Active to Precharge Delay
Reset value is five cycles.
This field defines the delay between an Activate command and a Precharge command in number of cycles. Number of cycles is
between 0 and 15.
• TRCD: Row to Column Delay
Reset value is two cycles.
This field defines the delay between an Activate command and a Read/Write command in number of cycles. Number of cycles
is between 0 and 15.
• TRP: Row Precharge Delay
Reset value is three cycles.
This field defines the delay between a Precharge command and another command in number of cycles. Number of cycles is
between 0 and 15.
• TRC: Row Cycle Delay
Reset value is seven cycles.
This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 0
and 15.
• TWR: Write Recovery Delay
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
• DBW: Data Bus Width
Reset value is 16 bits.
0: Reserved.
1: Data bus width is 16 bits.
31
30
29
28
27
26
25
24
TXSR
TRAS
23
22
21
20
19
18
17
16
TRCD
TRP
15
14
13
12
11
10
9
8
TRC
TWR
7
6
5
4
3
2
1
0
DBW
CAS
NB
NR
NC