Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Fiche De Données

32072H–AVR32–10/2012

programmed to zero in the end of block interrupt service routine that services the next-to-last
block transfer. This puts the DMACA into Row 1 state.

For rows 6, 8, and 10 (both CFGx.RELOAD_SR and CFGx.RELOAD_DS cleared) the user must
setup the last block descriptor in memory such that both LLI.CTLx.LLP_S_EN and
LLI.CTLx.LLP_D_EN are zero. If the LLI.LLPx register of the last block descriptor in memory is
non-zero, then the DMA transfer is terminated in Row 5. If the LLI.LLPx register of the last block
descriptor in memory is zero, then the DMA transfer is terminated in Row 1. 

For rows 7 and 9, the end-of-block interrupt service routine that services the next-to-last block
transfer should clear the CFGx.RELOAD_SR and CFGx.RELOAD_DS reload bits. The last
block descriptor in memory should be set up so that both the LLI.CTLx.LLP_S_EN and
LLI.CTLx.LLP_D_EN are zero. If the LLI.LLPx register of the last block descriptor in memory is
non-zero, then the DMA transfer is terminated in Row 5. If the LLI.LLPx register of the last block
descriptor in memory is zero, then the DMA transfer is terminated in Row 1.

Note:

The only allowed transitions between the rows of 

are from any row into 

row 1 or row 5. As already stated, a transition into row 1 or row 5 is used to terminate the DMA 
transfer. All other transitions between rows are not allowed. Software must ensure that illegal tran-
sitions between rows do not occur between blocks of a multi-block transfer. For example, if block N 
is in row 10 then the only allowed rows for block N + 1 are rows 10, 5 or 1.

Three registers, the LLPx, the CTLx and CFGx, need to be programmed to set up whether single
or multi-block transfers take place, and which type of multi-block transfer is used. The different
transfer types are shown in 

The “Update Method” column indicates where the values of SARx, DARx, CTLx, and LLPx are
obtained for the next block transfer when multi-block DMACA transfers are enabled.

Note:

In 

, all other combinations of LLPx.LOC = 0, CTLx.LLP_S_EN, 

CFGx.RELOAD_SR, CTLx.LLP_D_EN, and CFGx.RELOAD_DS are illegal, and causes indeter-
minate or erroneous behavior.

 is also a single block transfer.

1.

Read the Channel Enable register to choose a free (disabled) channel.

2.

Clear any pending interrupts on the channel from the previous DMA transfer by writing 
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, 
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that 
all interrupts have been cleared.

3.

Program the following channel registers:

a.

Write the starting source address in the SARx register for channel x.

b.

Write the starting destination address in the DARx register for channel x.

c.

Program CTLx and CFGx according to Row 1 as shown in 

Program the LLPx register with ‘0’.

d.

Write the control information for the DMA transfer in the CTLx register for channel 
x. For example, in the register, you can program the following:

– i. Set up the transfer type (memory or non-memory peripheral for source and 

destination) and flow control device by programming the TT_FC of the CTLx register.