Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Fiche De Données

32072H–AVR32–10/2012

responds to the OUT/DATA transaction with an ACK handshake when the endpoint accepted
the data successfully and has room for another data payload (the second bank is free).

This error exists only for isochronous IN/OUT endpoints. It set the Underflow Interrupt
(UNDERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Underflow Interrupt Enable
(UNDERFE) bit is one.

An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-
length packet is then automatically sent by the USBB.

An underflow can not occur during OUT stage on a CPU action, since the user may read only if
the bank is not empty (RXOUTI is one or RWALL is one).

An underflow can also occur during OUT stage if the host sends a packet while the bank is
already full. Typically, the CPU is not fast enough. The packet is lost.

An underflow can not occur during IN stage on a CPU action, since the user may write only if the
bank is not full (TXINI is one or RWALL is one).

This error exists for all endpoint types. It set the Overflow interrupt (OVERFI) bit in UESTAn,
what triggers an EPnINT interrupt if the Overflow Interrupt Enable (OVERFE) bit is one.

An overflow can occur during OUT stage if the host attempts to write into a bank that is too small
for the packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had
occurred. The bank is filled with all the first bytes of the packet that fit in.

An overflow can not occur during IN stage on a CPU action, since the user may write only if the
bank is not full (TXINI is one or RWALL is one).

This error exists only for high-bandwidth isochronous IN endpoints if the high-bandwidth isochro-
nous feature is supported by the device (see the UFEATURES register for this). 

At the end of the micro-frame, if at least one packet has been sent to the host, if less banks than
expected has been validated (by clearing the FIFOCON) for this micro-frame, it set the
HBISOINERRORI bit in UESTAn, what triggers an EPnINT interrupt if the High Bandwidth Iso-
chronous IN Error Interrupt Enable (HBISOINERRORE) bit is one.

For instance, if the Number of Transaction per MicroFrame for Isochronous Endpoint
(NBTRANS field in UECFGn is three (three transactions per micro-frame), only two banks are
filled by the CPU (three expected) for the current micro-frame. Then, the HBISOINERRI interrupt
is generated at the end of the micro-frame. Note that an UNDERFI interrupt is also generated
(with an automatic zero-length-packet), except in the case of a missing IN token.

This error exists only for high-bandwidth isochronous IN endpoints if the high-bandwidth isochro-
nous feature is supported by the device (see the UFEATURES register for this).

At the end of the micro-frame, if at least one packet has been sent to the host, if there is missing
IN token during this micro-frame, the bank(s) destined to this micro-frame is/are flushed out to
ensure a good data synchronization between the host and the device.