Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Fiche De Données

32072H–AVR32–10/2012

At block level, input clock signals of each channel can either be connected to the external inputs
TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for
chaining by writing to the BMR register. See 

Each channel can independently select an internal or external clock source for its counter:

• Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, 

TIMER_CLOCK4, TIMER_CLOCK5. See the Module Configuration Chapter for details about 
the connection of these clock sources.

• External clock signals: XC0, XC1 or XC2. See the Module Configuration Chapter for details 

about the connection of these clock sources.

This selection is made by the Clock Selection field in the Channel n Mode Register
(CMRn.TCCLKS).

The selected clock can be inverted with the Clock Invert bit in CMRn (CMRn.CLKI). This allows
counting on the opposite edges of the clock.

The burst function allows the clock to be validated when an external signal is high. The Burst
Signal Selection field in the CMRn register (CMRn.BURST) defines this signal.

Note:

In all cases, if an external clock is used, the duration of each of its levels must be longer than the 
CLK_TC period. The external clock frequency must be at least 2.5 times lower than the CLK_TC.

Figure 28-2. Clock Selection

The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped. See 

TIMER_CLOCK5

XC2

TCCLKS

CLKI

BURST

1

Selected

Clock

XC1

XC0

TIMER_CLOCK4

TIMER_CLOCK3

TIMER_CLOCK2

TIMER_CLOCK1