Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Fiche De Données
Codes de produits
AT32UC3A3-XPLD
799
32072H–AVR32–10/2012
AT32UC3A3
29.7.2
Mode Register
Name:
MR
Access Type:
Read/Write
Offset:
0x04
Reset Value:
0x00000000
• SHTIM: Sample & Hold Time
Sample & Hold Time = (SHTIM+3) / ADCClock
• STARTUP: Start Up Time
Startup Time = (STARTUP+1) * 8 / ADCClock
This Time should respect a minimal value. Refer to Electrical Characteristics section for details.
• PRESCAL: Prescaler Rate Selection
ADCClock = CLK_ADC / ( (PRESCAL+1) * 2 )
• SLEEP: Sleep Mode
1: Sleep Mode is selected.
0: Normal Mode is selected.
• LOWRES: Resolution
1: 8-bit resolution is selected.
0: 10-bit resolution is selected.
• TRGSEL: Trigger Selection
• TRGEN: Trigger Enable
1: The hardware trigger selected by the TRGSEL field is enabled.
0: The hardware triggers are disabled. Starting a conversion is only possible by software.
31
30
29
28
27
26
25
24
–
–
–
–
SHTIM
23
22
21
20
19
18
17
16
–
STARTUP
15
14
13
12
11
10
9
8
PRESCAL
7
6
5
4
3
2
1
0
–
–
SLEEP
LOWRES
TRGSEL
TRGEN
TRGSEL
Selected TRGSEL
0
0
0
Internal Trigger 0, depending of chip integration
0
0
1
Internal Trigger 1, depending of chip integration
0
1
0
Internal Trigger 2, depending of chip integration
0
1
1
Internal Trigger 3, depending of chip integration
1
0
0
Internal Trigger 4, depending of chip integration
1
0
1
Internal Trigger 5, depending of chip integration
1
1
0
External trigger