Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Fiche De Données
Codes de produits
AT32UC3A3-XPLD
841
32072H–AVR32–10/2012
AT32UC3A3
31.6.8.3
Write Access
During a write access, the SR.XFRDONE bit behaves as shown in
Figure 31-14. SR.XFRDONE During a Write Access
31.7
User Interface
Table 31-7.
MCI Register Memory Map
Offset
Register
Name
Access
Reset
0x000
Control Register
CR
Write-only
0x00000000
0x004
Mode Register
MR
Read-write
0x00000000
0x008
Data Time-out Register
DTOR
Read-write
0x00000000
0x00C
SD/SDIO Card Register
SDCR
Read-write
0x00000000
0x010
Argument Register
ARGR
Read-write
0x00000000
0x014
Command Register
CMDR
Write-only
0x00000000
0x018
Block Register
BLKR
Read-write
0x00000000
0x01C
Completion Signal Time-out Register
CSTOR
Read-write
0x00000000
0x020
Response Register
RSPR
Read-only
0x00000000
0x024
Response Register
RSPR1
Read-only
0x00000000
0x028
Response Register
RSPR2
Read-only
0x00000000
0x02C
Response Register
RSPR3
Read-only
0x00000000
0x030
Receive Data Register
RDR
Read-only
0x00000000
0x034
Transmit Data Register
TDR
Write-only
0x00000000
0x040
Status Register
SR
Read-only
0x0C000025
CMD line
MCI writeCMD
Card response
CMDRDY flag
Data bus - D0
1st Block
Not busy flag
XFRDONE flag
The CMDRDY flag is released 8 t
bit
lafter the end of the card response.
Last Block
D0
1st Block
Last Block
D0 is tied by the card
D0 is released