Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Fiche De Données
Codes de produits
ATEVK1105
437
AT32UC3A
29. Ethernet MAC (MACB)
Rev: 1.1.2.5
29.1
Features
•
Compatible with IEEE Standard 802.3
•
10 and 100 Mbit/s Operation
•
Full- and Half-duplex Operation
•
Statistics Counter Registers
•
MII/RMII Interface to the Physical Layer
•
Interrupt Generation to Signal Receive and Transmit Completion
•
DMA Master on Receive and Transmit Channels
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Transmit and Receive FIFOs
•
Automatic Pad and CRC Generation on Transmitted Frames
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Automatic Discard of Frames Received with Errors
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Address Checking Logic Supports Up to Four Specific 48-bit Addresses
•
Supports Promiscuous Mode Where All Valid Received Frames are Copied to Memory
•
Hash Matching of Unicast and Multicast Destination Addresses
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External Address Matching of Received Frames
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Physical Layer Management through MDIO Interface
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Half-duplex Flow Control by Forcing Collisions on Incoming Frames
•
Full-duplex Flow Control with Recognition of Incoming Pause Frames and Hardware
Generation
of Transmitted Pause Frames
•
Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and
Priority Tagged
Frames
•
Multiple Buffers per Receive and Transmit Frame
•
Wake-on-LAN Support
•
Jumbo Frames Up to 10240 bytes Supported
29.2
Description
The MACB module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 stan-
dard using an address checker, statistics and control registers, receive and transmit blocks, and
a DMA interface.
The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash regis-
The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash regis-
ter for matching multicast and unicast addresses. It can recognize the broadcast address of all
ones, copy all frames, and act on an external address match signal.
The statistics register block contains registers for counting various types of events associated
The statistics register block contains registers for counting various types of events associated
with transmit and receive operations. These registers, along with the status words stored in the
receive buffer list, enable software to generate network management statistics compatible with
IEEE 802.3.
32058K
AVR32-01/12