Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
14
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HEET]
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6.
I/O Multiplexing and Considerations
6.1
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C,
D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin
(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral
Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.
D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin
(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral
Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.
describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1.
PORT Function Multiplexing
Pin
I/O Pin Supply Type
A
B
C
D
E
F
G
H
SAMD21E SAMD21GSAMD21J
EIC
REF
ADC
AC
PTC
DAC SERCOM
SERCOM-
ALT
TC
(3)
/
TCC
TCC
COM
AC/GCLK
1
1
1
PA00
VDDANA
EXTINT[0]
SERCOM1/
PAD[0]
TCC2/WO[0]
2
2
2
PA01
VDDANA
EXTINT[1]
SERCOM1/
PAD[1]
TCC2/WO[1]
3
3
3
PA02
VDDANA
EXTINT[2]
AIN[0]
Y[0]
VOUT
4
4
4
PA03
VDDANA
EXTINT[3]
ADC/VREFA
DAC/VREFA
DAC/VREFA
AIN[1]
Y[1]
5
PB04
VDDANA
EXTINT[4]
AIN[12]
Y[10]
6
PB05
VDDANA
EXTINT[5]
AIN[13]
Y[11]
9
PB06
VDDANA
EXTINT[6]
AIN[14]
Y[12]
10
PB07
VDDANA
EXTINT[7]
AIN[15]
Y[13]
7
11
PB08
VDDANA
EXTINT[8]
AIN[2]
Y[14]
SERCOM4/
PAD[0]
TC4/WO[0]
8
12
PB09
VDDANA
EXTINT[9]
AIN[3]
Y[15]
SERCOM4/
PAD[1]
TC4/WO[1]
5
9
13
PA04
VDDANA
EXTINT[4]
ADC/VREFB
AIN[4]
AIN[0]
Y[2]
SERCOM0/
PAD[0]
TCC0/WO[0]
6
10
14
PA05
VDDANA
EXTINT[5]
AIN[5]
AIN[1]
Y[3]
SERCOM0/
PAD[1]
TCC0/WO[1]
7
11
15
PA06
VDDANA
EXTINT[6]
AIN[6]
AIN[2]
Y[4]
SERCOM0/
PAD[2]
TCC1/WO[0]
8
12
16
PA07
VDDANA
EXTINT[7]
AIN[7]
AIN[3]
Y[5]
SERCOM0/
PAD[3]
TCC1/WO[1]
I2S/SD[0]
11
13
17
PA08
VDDIO
I
2
C
NMI
AIN[16]
X[0]
SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TCC0/WO[0]
TCC1/
WO[2]
WO[2]
I2S/SD[1]
12
14
18
PA09
VDDIO
I
2
C
EXTINT[9]
AIN[17]
X[1]
SERCOM0/
PAD[1]
SERCOM2/
PAD[1]
TCC0/WO[1]
TCC1/
WO[3]
WO[3]
I2S/
MCK[0]
13
15
19
PA10
VDDIO
EXTINT[10]
AIN[18]
X[2]
SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TCC1/WO[0]
TCC0/
WO[2]
WO[2]
I2S/
SCK[0]
GCLK_IO[4]
14
16
20
PA11
VDDIO
EXTINT[11]
AIN[19]
X[3]
SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TCC1/WO[1]
TCC0/
WO[3]
WO[3]
I2S/FS[0] GCLK_IO[5]