Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
166
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
16.8.3 Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x08
Reset:
0x00000000
Property:
-
Note:
Depending on the fuse settings, various bits of the INTFLAG register can be set to one at startup. Therefore the
user should clear those bits before using the corresponding interrupts.
user should clear those bits before using the corresponding interrupts.
z
Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 17 – DPLLLTO: DPLL Lock Timeout
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Timeout bit in the Status register (PCLKSR.DPLLLTO)
and will generate an interrupt request if INTENSET.DPLLLTO is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DPLL Lock Timeout interrupt flag.
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Timeout bit in the Status register (PCLKSR.DPLLLTO)
and will generate an interrupt request if INTENSET.DPLLLTO is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DPLL Lock Timeout interrupt flag.
z
Bit 16 – DPLLLCKF: DPLL Lock Fall
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Fall bit in the Status register (PCLKSR.DPLLLCKF)
and will generate an interrupt request if INTENSET.DPLLLCKF is one.
Writing a zero to this bit has no effect.
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Fall bit in the Status register (PCLKSR.DPLLLCKF)
and will generate an interrupt request if INTENSET.DPLLLCKF is one.
Writing a zero to this bit has no effect.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DPLLLTO
DPLLLCKF
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DPLLLCKR
B33SRDY
BOD33DET
BOD33RDY
DFLLRCS
Access
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DFLLLCKC
DFLLLCKF
DFLLOOB
DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0