Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données

Codes de produits
ATSAMD21-XPRO
Page de 1018
184
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
16.8.10 DFLL48M Control
Name:
DFLLCTRL
Offset:
0x24
Reset:
0x0080
Property:
Write-Protected, Write-Synchronized
z
Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.
z
Bit 11 – WAITLOCK: Wait Lock
This bit controls the DFLL output clock, depending on lock status:
0: Output clock before the DFLL is locked.
1: Output clock when DFLL is locked.
z
Bit 10 – BPLCKC: Bypass Coarse Lock
This bit controls the coarse lock procedure:
0: Bypass coarse lock is disabled.
1: Bypass coarse lock is enabled.
z
Bit 9 – QLDIS: Quick Lock Disable
0: Quick Lock is enabled.
1: Quick Lock is disabled.
z
Bit 8 – CCDIS: Chill Cycle Disable
0: Chill Cycle is enabled.
1: Chill Cycle is disabled.
z
Bit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock 
requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will 
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, 
the oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the DFLLCTRL.RUNSTDBY bit is one. If 
DFLLCTRL.RUNSTDBY is zero, the oscillator is disabled.
0: The oscillator is always on, if enabled.
Bit
15
14
13
12
11
10
9
8
WAITLOCK
BPLCKC
QLDIS
CCDIS
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ONDEMAND
RUNSTDBY
USBCRM
LLAW
STABLE
MODE
ENABLE
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset
1
0
0
0
0
0
0
0