Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
199
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
16.8.20 DPLL Status
Name:
DPLLSTATUS
Offset:
0x50
Reset:
0x00
Property:
-
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 3 – DIV: Divider Enable
0: The reference clock divider is disabled.
1: The reference clock divider is enabled.
0: The reference clock divider is disabled.
1: The reference clock divider is enabled.
z
Bit 2 – ENABLE: DPLL Enable
0: The DPLL is disabled.
1: The DPLL is enabled.
0: The DPLL is disabled.
1: The DPLL is enabled.
z
Bit 1 – CLKRDY: Output Clock Ready
0: The DPLL output clock is off
1: The DPLL output clock in on.
0: The DPLL output clock is off
1: The DPLL output clock in on.
z
Bit 0 – LOCK: DPLL Lock Status
0: The DPLL Lock signal is cleared.
1: The DPLL Lock signal is asserted.
0: The DPLL Lock signal is cleared.
1: The DPLL Lock signal is asserted.
Bit
7
6
5
4
3
2
1
0
DIV
ENABLE
CLKRDY
LOCK
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0