Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
209
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
17.8.1 Control
Name:
CTRL
Offset:
0x0
Reset:
0xXX
Property:
Enable-Protected, Write-Protected, Write-Synchronized
z
Bit 7 – ALWAYSON: Always-On
This bit allows the WDT to run continuously. After being written to one, this bit cannot be written to zero, and the
WDT will remain enabled until a power-on reset is received. When this bit is one, the Control register (CTRL), the
Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any
writes to these registers are not allowed. Writing a zero to this bit has no effect.
0: The WDT is enabled and disabled through the ENABLE bit.
1: The WDT is enabled and can only be disabled by a power-on reset (POR).
This bit is not enable-protected.
This bit is loaded from NVM User Row at startup. Refer to
This bit allows the WDT to run continuously. After being written to one, this bit cannot be written to zero, and the
WDT will remain enabled until a power-on reset is received. When this bit is one, the Control register (CTRL), the
Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any
writes to these registers are not allowed. Writing a zero to this bit has no effect.
0: The WDT is enabled and disabled through the ENABLE bit.
1: The WDT is enabled and can only be disabled by a power-on reset (POR).
This bit is not enable-protected.
This bit is loaded from NVM User Row at startup. Refer to
for more details.
z
Bits 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – WEN: Watchdog Timer Window Mode Enable
This bit enables window mode.
This bit can only be written when CTRL.ENABLE is zero or CTRL.ALWAYSON is one:
This bit enables window mode.
This bit can only be written when CTRL.ENABLE is zero or CTRL.ALWAYSON is one:
z
When CTRL.ALWAYSON=0, this bit is enable-protected by CTRL.ENABLE.
z
When CTRL.ALWAYSON=1 this bit is not enable-protected by CTRL.ENABLE.
The initial value of this bit is loaded from Flash Calibration.
0: Window mode is disabled (normal operation).
1: Window mode is enabled.
This bit is loaded from NVM User Row at startup. Refer to
0: Window mode is disabled (normal operation).
1: Window mode is enabled.
This bit is loaded from NVM User Row at startup. Refer to
for more details.
z
Bit 1 – ENABLE: Enable
This bit enables or disables the WDT. Can only be written while CTRL.ALWAYSON is zero.
0: The WDT is disabled.
1: The WDT is enabled.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
This bit is loaded from NVM User Row at startup. Refer to
This bit enables or disables the WDT. Can only be written while CTRL.ALWAYSON is zero.
0: The WDT is disabled.
1: The WDT is enabled.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
This bit is loaded from NVM User Row at startup. Refer to
for more details.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit
7
6
5
4
3
2
1
0
ALWAYSON
WEN
ENABLE
Access
R/W
R
R
R
R
R/W
R/W
R
Reset
X
0
0
0
0
X
X
0