Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

The DMAC consists of a DMA module and a CRC module.

The DMAC can, without interaction from the CPU, transfer data between peripherals and memories. The data transferred 
by the DMAC are called transactions, and these transactions can be split into smaller data transfers. 

 shows 

the relationship between the different transfer sizes.

z

Beat transfer: Defined as the size of one data transfer bus access, and the size is selected by writing the Beat Size 
bit group in the Block Transfer Control register (

.BEATSIZE)

z

Burst transfer: Defined as n beat transfers, where n will differ from one device family to another. For this device 
family, n is 1. A burst transfer is atomic, and cannot be interrupted.

z

Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k 
beats. In contrast to the burst transfer, a block transfer can be interrupted.

z

Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second 
and so forth, as shown in 

. A DMA transaction is defined as all block transfers within a linked list, being 

completed.

A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must remain in SRAM. For 
further details on the transfer descriptor refer to 

.

 shows several block transfers linked together, which are called linked descriptors. For further information 

.

A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be configured to 
be either a software trigger, an event trigger or one of the dedicated peripheral triggers. The transfer trigger will result in 
a DMA transfer request from the specific channel to the arbiter, and if there are several DMA channels with pending 
transfer requests, the arbiter has to choose which channel to grant access to become the active channel. The DMA 
channel granted access as the active channel will carry out the transaction as configured in the transfer descriptor. The 
DMA channel can be interrupted by a higher prioritized channel after each burst transfer, but will resume its block 
transfer when it is granted access as the active channel again.

For each beat transfer an optional output event can be generated, and for each block transfer optional interrupts and an 
optional output event can be generated. When a transaction is completed, dependent of the configuration, the DMA 
channel will either be suspended or disabled.

The internal CRC supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). It 
can be used with selectable DMA channel or independently, with I/O interface.