Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
314
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
19.8.1.20 Channel Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Channel Interrupt Enable Set (
will also be reflected in the Channel Interrupt Enable Set (
) register.
Name:
CHINTENCLR
Offset:
0x4C
Reset:
0x00
Property:
Write-Protected
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – SUSP: Channel Suspend Interrupt Enable
0: The Channel Suspend interrupt is disabled.
1: The Channel Suspend interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend
interrupt.
0: The Channel Suspend interrupt is disabled.
1: The Channel Suspend interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend
interrupt.
z
Bit 1 – TCMPL: Transfer Complete Interrupt Enable
0: The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag will not
be set when a block transfer is completed.
1: The Channel Transfer Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel
Transfer Complete interrupt.
0: The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag will not
be set when a block transfer is completed.
1: The Channel Transfer Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel
Transfer Complete interrupt.
z
Bit 0 – TERR: Transfer Error Interrupt Enable
0: The Channel Transfer Error interrupt is disabled.
1: The Channel Transfer Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel
Transfer Error interrupt.
0: The Channel Transfer Error interrupt is disabled.
1: The Channel Transfer Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel
Transfer Error interrupt.
Bit
7
6
5
4
3
2
1
0
SUSP
TCMPL
TERR
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0