Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
361
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
21.8.5 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name:
INTENSET
Offset:
0x10
Reset:
0x00
Property:
Write-Protected
z
Bits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – ERROR: Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit sets the ERROR interrupt enable.
This bit will read as the current value of the ERROR interrupt enable.
Writing a zero to this bit has no effect.
Writing a one to this bit sets the ERROR interrupt enable.
This bit will read as the current value of the ERROR interrupt enable.
z
Bit 0 – READY: NVM Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit sets the READY interrupt enable.
This bit will read as the current value of the READY interrupt enable.
Writing a zero to this bit has no effect.
Writing a one to this bit sets the READY interrupt enable.
This bit will read as the current value of the READY interrupt enable.
Bit
7
6
5
4
3
2
1
0
ERROR
READY
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0