Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
411
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
23.8.4 Channel Status
Name:
CHSTATUS
Offset:
0x0C
Reset:
0x000F00FF
Property:
-
z
Bits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 27:24 – CHBUSYx [x=11..8]: Channel x Busy
This bit is cleared when channel x is idle
This bit is set if an event on channel x has not been handled by all event users connected to channel x.
This bit is cleared when channel x is idle
This bit is set if an event on channel x has not been handled by all event users connected to channel x.
z
Bits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 19:16 – USRRDYx [x=11..8]: Channel x User Ready
This bit is cleared when at least one of the event users connected to the channel is not ready.
This bit is set when all event users connected to channel x are ready to handle incoming events on channel x.
This bit is cleared when at least one of the event users connected to the channel is not ready.
This bit is set when all event users connected to channel x are ready to handle incoming events on channel x.
z
Bits 15:8 – CHBUSYx [x=7..0]: Channel x Busy
This bit is cleared when channel x is idle
This bit is set if an event on channel x has not been handled by all event users connected to channel x.
This bit is cleared when channel x is idle
This bit is set if an event on channel x has not been handled by all event users connected to channel x.
Bit
31
30
29
28
27
26
25
24
CHBUSY11
CHBUSY10
CHBUSY9
CHBUSY8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
USRRDY11
USRRDY10
USRRDY9
USRRDY8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
1
1
1
1
Bit
15
14
13
12
11
10
9
8
CHBUSY7
CHBUSY6
CHBUSY5
CHBUSY4
CHBUSY3
CHBUSY2
CHBUSY1
CHBUSY0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
USRRDY7
USRRDY6
USRRDY5
USRRDY4
USRRDY3
USRRDY2
USRRDY1
USRRDY0
Access
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
1
1