Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
428
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
25.
SERCOM USART – SERCOM Universal Synchronous and Asynchronous
Receiver and Transmitter
Receiver and Transmitter
25.1 Overview
The universal synchronous and asynchronous receiver and transmitter (USART) is one of the available modes in the
Serial Communication Interface (SERCOM).
Serial Communication Interface (SERCOM).
Refer to
for details.
The USART uses the SERCOM transmitter and receiver configured as shown in
. Fields shown in capital
letters are synchronous to the CLK_SERCOMx_APB and accessible by the CPU, while fields with lowercase letters can
be configured to run on the internal generic clock or an external clock.
be configured to run on the internal generic clock or an external clock.
The transmitter consists of a single write buffer, a shift register and control logic for handling different frame formats. The
write buffer allows continuous data transmission without any delay between frames.
write buffer allows continuous data transmission without any delay between frames.
The receiver consists of a two-level receive buffer and a shift register. Status information for the received data is
available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during
asynchronous data reception.
available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during
asynchronous data reception.
25.2 Features
z
Full-duplex operation
z
Asynchronous (with clock reconstruction) or synchronous operation
z
Internal or external clock source for asynchronous and synchronous operation
z
Baud-rate generator
z
Supports serial frames with 5, 6, 7, 8 or 9 data bits and 1 or 2 stop bits
z
Odd or even parity generation and parity check
z
Selectable LSB- or MSB-first data transfer
z
Buffer overflow and frame error detection
z
Noise filtering, including false start-bit detection and digital low-pass filter
z
Collision detection
z
Can operate in all sleep modes
z
Operation at speeds up to half the system clock for internally generated clocks
z
Operation at speeds up to the system clock for externally generated clocks
z
RTS and CTS flow control
z
IrDA modulation and demodulation up to 115.2 kbps
z
LIN slave support
z
Auto-baud and break character detection
z
Start-of-frame detection
z
Can be used with DMA