Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

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Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when 
DATA is read.

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Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when 
DATA is written.

The USART has the following interrupt sources: 

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Error (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.

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Received Break (RXBRK): this is an asynchronous interrupt and can be used to wake-up the device from any 
sleep mode.

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Clear to Send Input Change (CTSIC): this is an asynchronous interrupt and can be used to wake-up the device 
from any sleep mode.

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Receive Start (RXS): this is an asynchronous interrupt and can be used to wake-up the device from any sleep 
mode.

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Receive Complete (RXC): this is an asynchronous interrupt and can be used to wake-up the device from any sleep 
mode.

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Transmit Complete (TXC): this is an asynchronous interrupt and can be used to wake-up the device from any 
sleep mode.

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Data Register Empty (DRE): this is an asynchronous interrupt and can be used to wake-up the device from any 
sleep mode.

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear 
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one 
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the 
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt 
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is 
cleared, the interrupt is disabled or the USART is reset. See the register description for details on how to clear interrupt 
flags. 

The USART has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to 
determine which interrupt condition is present.

Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to 

Not applicable.

When using internal clocking, writing the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) to one will 
allow GCLK_SERCOMx_CORE to be enabled in all sleep modes. Any interrupt can wake up the device.

When using external clocking, writing a one to CTRLA.RUNSTDBY will allow the Receive Start or Receive Complete 
interrupt.to wake up the device. 

If CTRLA.RUNSTDBY is zero, the internal clock will be disabled when any ongoing transfer is finished. A Receive Start 
or Transfer Complete interrupt can wake up the device. When using external clocking, this will be disconnected when any 
ongoing transfer is finished, and all reception will be dropped.

Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be 
synchronized when accessed. A register can require:

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Synchronization when written

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Synchronization when read