Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
487
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
26.8.4 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x14
Reset:
0x00
Property:
Write-Protected
z
Bit 7– ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
z
Bits 6:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 3– SSL: Slave Select Low Interrupt Enable
0: Slave Select Low interrupt is disabled.
1: Slave Select Low interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Slave Select Low Interrupt Enable bit, which disables the Slave Select Low
interrupt.
0: Slave Select Low interrupt is disabled.
1: Slave Select Low interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Slave Select Low Interrupt Enable bit, which disables the Slave Select Low
interrupt.
z
Bit 2 – RXC: Receive Complete Interrupt Enable
0: Receive Complete interrupt is disabled.
1: Receive Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
0: Receive Complete interrupt is disabled.
1: Receive Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
z
Bit 1 – TXC: Transmit Complete Interrupt Enable
0: Transmit Complete interrupt is disabled.
1: Transmit Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit Complete
interrupt.
0: Transmit Complete interrupt is disabled.
1: Transmit Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit Complete
interrupt.
z
Bit 0 – DRE: Data Register Empty Interrupt Enable
0: Data Register Empty interrupt is disabled.
1: Data Register Empty interrupt is enabled.
Writing a zero to this bit has no effect.
0: Data Register Empty interrupt is disabled.
1: Data Register Empty interrupt is enabled.
Writing a zero to this bit has no effect.
Bit
7
6
5
4
3
2
1
0
ERROR
SSL
RXC
TXC
DRE
Access
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0