Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données

511

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

2

The I

2

C slave is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by 

automatic handling of most events. Auto triggering of operations and a special smart mode, which can be enabled by 
writing a 1 to the Smart Mode Enable bit in the Control A register (CTRLA.SMEN), are included to reduce software’s 
complexity and code size.

The I

2

C slave has two interrupt strategies. When SCL Stretch Mode (CTRLA.SCLSM) is set to zero, SCL is stretched 

before or after the acknowledge bit. In this mode, the I

2

C slave operates according to the behavior diagram shown in 

. The circles with a capital S followed by a number (S1, S2... etc.) indicate which node in the figure the bus 

logic can jump to based on software or hardware interaction.

This diagram is used as reference for the description of the I

2

C slave operation throughout the document. 

In the second strategy (SCLSM=1), interrupts only occur after the ACK bit as shown in 

. This strategy can be 

used when it is not necessary to check DATA before acknowledging. For master reads, an address and data interrupt will 
be issued simultaneously after the address acknowledge, while for master writes, the first data interrupt will be seen after 
the first data byte has been received by the slave and the acknowledge bit has been sent to the master.

Note that setting SCLSM to 1 is required for High-speed mode.

Interrupt on STOP 
Condition Enabled

Software interaction

The master provides data 
on the bus

Addressed slave provides 
data on the bus