Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
544
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
27.8.2.2 Control B
Name:
CTRLB
Offset:
0x04
Reset:
0x00000000
Property:
Write-Protected, Enable-Protected, Write-Synchronized
z
Bits 31:19 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 18 – ACKACT: Acknowledge Action
The Acknowledge Action (ACKACT) bit defines the I
The Acknowledge Action (ACKACT) bit defines the I
2
C master's acknowledge behavior after a data byte is
received from the I
2
C slave. The acknowledge action is executed when a command is written to CTRLB.CMD, or if
smart mode is enabled (CTRLB.SMEN is written to one), when DATA.DATA is read.
0: Send ACK.
1: Send NACK.
This bit is not enable-protected.
This bit is not write-synchronized.
0: Send ACK.
1: Send NACK.
This bit is not enable-protected.
This bit is not write-synchronized.
z
Bits 17:16 – CMD[1:0]: Command
Writing the Command bits (CMD) triggers the master operation as defined in
Writing the Command bits (CMD) triggers the master operation as defined in
. The CMD bits are
strobe bits, and always read as zero. The acknowledge action is only valid in master read mode. In master write
mode, a command will only result in a repeated start or stop condition. The CTRLB.ACKACT bit and the CMD bits
mode, a command will only result in a repeated start or stop condition. The CTRLB.ACKACT bit and the CMD bits
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
ACKACT
CMD[1:0]
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
QCEN
SMEN
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0