Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
548
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
27.8.2.4 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x14
Reset:
0x00
Property:
Write-Protected
z
Bit 7– ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
z
Bits 6:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – SB: Slave on Bus Interrupt Enable
0: The Slave on Bus interrupt is disabled.
1: The Slave on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Slave on Bus Interrupt Enable bit, which disables the Slave on Bus interrupt.
0: The Slave on Bus interrupt is disabled.
1: The Slave on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Slave on Bus Interrupt Enable bit, which disables the Slave on Bus interrupt.
z
Bit 0 – MB: Master on Bus Interrupt Enable
0: The Master on Bus interrupt is disabled.
1: The Master on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Master on Bus Interrupt Enable bit, which disables the Master on Bus
interrupt.
0: The Master on Bus interrupt is disabled.
1: The Master on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Master on Bus Interrupt Enable bit, which disables the Master on Bus
interrupt.
Bit
7
6
5
4
3
2
1
0
ERROR
SB
MB
Access
R/W
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0