Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

For two PDM microphones, the I

2

S controller should be configured in PDM2 mode with one slot and 32-bit Datasize. The 

Serializer will store 16 samples of each microphone in one half of the data word, with left microphone bits in lower half 
and right microphone bits in upper half, like in compact stereo format. 

Based on oversampling frequency requirement from PDM microphone, SCKn frequency must be configured in I

2

S 

controller.

Let us consider a microphone that requires a Sampling frequency (fs) of 48kHz and Oversampling frequency of 64fs. 
The, SCKn frequency should be 3.072MHz.

After selecting proper GCLK_I2S_n and MCKDIV, SCKn must be selected as per required frequency.  

In PDM mode, only the clock and data line (SCKn and  SDn) pins are used.          

To configure PDM2 mode, set SLOTSIZE = 0x01 (16-bits), NBSLOTS = 0x00 (1 slots) and SERCTRL0.DATASIZE = 
0x00 (32-bit).

To allow more flexibility, data words received by Serializer m will be formatted by the Receive Formatting Unit before 
being stored into the Data Holding register (DATAm). The data words written into DATAm register will be formatted by 
the Transmit Formatting Unit before transmission by Serializer m.

The formatting options are defined in SERCTRLm register:

z

SLOTADJ for left or right justification in the slot

z

BITREV for bit reversal

z

WORDADJ for left or right justification in the data word

z

EXTEND for extension to the word size

Each Serializer can be connected either to one single DMAC channel or to one DMAC channel per data slot in stereo 
mode. This is selected by writing the SERCTRLm.DMA bit.

The

 

I

2

S generates the following DMA requests:

z

If SERCTRLm.DMA=0, all data channels or slots use the I2S_DMAC_ID_RX_m DMA trigger for Receiver or the 
I2S_DMAC_ID_TX_m trigger for Transmitter.

z

If SERCTRLm.DMA=1, in Receiver mode, even-numbered slots use the I2S_DMAC_ID_RX_m DMA trigger and 
odd-numbered slots use the I2S_DMAC_ID_TX_m trigger.

z

If SERCTRLm.DMA=1, in Transmitter mode, even-numbered slots use the I2S_DMAC_ID_TX_m DMA trigger and 
odd-numbered slots use the I2S_DMAC_ID_RX_m trigger.

The DMAC reads from the DATAm register and writes to the DATAm register for all data slots, successively.

Receive Ready 

x

x

When data is read

Transmit Ready 
(Buffer empty)

x

x

When data is 

written

Receive Overrun

x

Transmit 
Underrun

x