Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
610
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
29.6.4.2 Interrupts
The TC has the following interrupt sources:
z
Overflow/Underflow: OVF. This is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
mode.
z
Compare or Capture Channel: MCx. This is an asynchronous interrupt and can be used to wake-up the device from
any sleep mode.
any sleep mode.
z
Capture Overflow Error: ERR. This is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
sleep mode.
z
Synchronization Ready: SYNCRDY. This is an asynchronous interrupt and can be used to wake-up the device from
any sleep mode.
any sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the TC is reset. See the
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the TC is reset. See the
The TC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to
determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be
generated. Refer to
determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be
generated. Refer to
for details.
29.6.4.3 Events
The TC can generate the following output events:
z
Overflow/Underflow (OVF)
z
Match or Capture (MC)
Writing a one to an Event Output bit in the Event Control register (EVCTRL.MCEO) enables the corresponding output
event. Writing a zero to this bit disables the corresponding output event.
event. Writing a zero to this bit disables the corresponding output event.
To enable one of the following event actions, write to the Event Action bit group (EVCTRL.EVACT).
z
Start the counter
z
Retrigger counter
z
Increment or decrement counter (depends on counter direction)
z
Capture event
z
Capture period
z
Capture pulse width
Writing a one to the TC Event Input bit in the Event Control register (EVCTRL.TCEI) enables input events to the TC.
Writing a zero to this bit disables input events to the TC. Refer to
Writing a zero to this bit disables input events to the TC. Refer to
for details on
configuring the Event System.
29.6.5 Sleep Mode Operation
The TC can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in the Control
A register (CTRLA.RUNSTDBY) must be written to one. The TC can wake up the device using interrupts from any sleep
mode or perform actions through the Event System.
A register (CTRLA.RUNSTDBY) must be written to one. The TC can wake up the device using interrupts from any sleep
mode or perform actions through the Event System.
29.6.6 Synchronization
Due to the asynchronicity between CLK_TCx_APB and GCLK_TCx some registers must be synchronized when
accessed. A register can require:
accessed. A register can require:
z
Synchronization when written
z
Synchronization when read
z
Synchronization when written and read