Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
676
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
30.8.1 Control A
Name:
CTRLA
Offset:
0x00
Reset:
0x00000000
Property:
Enable-Protected, Write-Protected, Write-Synchronized
z
Bits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 27:24 – CPTENx [x=3..0]: Capture Channel x Enable
These bits are used to select the capture or compare operation on channel x. The number of available channels
depend on the TCC instance.
Writing a one to CAPTENx enables capture on channel x.
Writing a zero to CAPTENx disables capture on channel x.
These bits are not synchronized.
These bits are used to select the capture or compare operation on channel x. The number of available channels
depend on the TCC instance.
Writing a one to CAPTENx enables capture on channel x.
Writing a zero to CAPTENx disables capture on channel x.
These bits are not synchronized.
z
Bits 23:15 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 14 – ALOCK: Auto Lock
When this bit is set, Lock Update (LUPD) is set to one on each overflow/underflow or re-trigger event.
0: The LUPD bit is not affected on overflow/underflow, and re-trigger event.
1: The LUPD bit is set on each overflow/underflow or re-trigger event.
When this bit is set, Lock Update (LUPD) is set to one on each overflow/underflow or re-trigger event.
0: The LUPD bit is not affected on overflow/underflow, and re-trigger event.
1: The LUPD bit is set on each overflow/underflow or re-trigger event.
Bit
31
30
29
28
27
26
25
24
CPTEN3
CPTEN2
CPTEN1
CPTEN0
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
ALOCK
PRESCSYNC[1:0]
RUNSTDBY
PRESCALER[2:0]
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RESOLUTION[1:0]
ENABLE
SWRST
Access
R
R/W
R/W
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0