Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
707
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
30.8.14 Status
Name:
STATUS
Offset:
0x30
Reset:
0x00000001
Property:
-
z
Bits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 27:24 – CMPx [x=3..0]: Compare Channel x Value
This bit reflects the channel x output compare value.
0: Channel compare output value is 0.
1: Channel compare output value is 1.
This bit reflects the channel x output compare value.
0: Channel compare output value is 0.
1: Channel compare output value is 1.
z
Bits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 19:16 – CCBVx [x=3..0]: Compare Channel x Buffer Valid
For a compare channel, the bit is set when a new value is written to the corresponding CCBx register. The bit is
cleared by writing a one to the corresponding location or automatically cleared on an UPDATE condition.
For a capture channel, the bit is set when a valid capture value is stored in the CCBx register. The bit is automati-
cally cleared when the CCx register is read.
For a compare channel, the bit is set when a new value is written to the corresponding CCBx register. The bit is
cleared by writing a one to the corresponding location or automatically cleared on an UPDATE condition.
For a capture channel, the bit is set when a valid capture value is stored in the CCBx register. The bit is automati-
cally cleared when the CCx register is read.
Bit
31
30
29
28
27
26
25
24
CMP3
CMP2
CMP1
CMP0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
CCBV3
CCBV2
CCBV1
CCBV0
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
FAULT1
FAULT0
FAULTB
FAULTA
FAULT1IN
FAULT0IN
FAULTBIN
FAULTAIN
Access
R/W
R/W
R/W
R/W
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PERBV
WAVEBV
PATTBV
SLAVE
DFS
IDX
STOP
Access
R/W
R/W
R/W
R
R/W
R
R
R
Reset
0
0
0
0
0
0
0
1