Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
724
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
30.8.21 Waveform Control Buffer
Name:
WAVEB
Offset:
0x68
Reset:
0x00000000
Property:
-
z
Bits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 27:24 – SWAPBx [x=3..0]: Swap DTI Output Pair x Buffer
These bits represent the SWAP buffers. When the double buffering is enable, SWAPB bits value is copied to the
SWAP bits on an UPDATE condition.
These bits represent the SWAP buffers. When the double buffering is enable, SWAPB bits value is copied to the
SWAP bits on an UPDATE condition.
z
Bits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 19:16 – POLBx [x=3..0]: Channel x Polarity Buffer
These bits represent the POL buffers. When the double buffering is enable, POLB bits value is copied to the POL
bits on an UPDATE condition.
These bits represent the POL buffers. When the double buffering is enable, POLB bits value is copied to the POL
bits on an UPDATE condition.
z
Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit
31
30
29
28
27
26
25
24
SWAPB3
SWAPB2
SWAPB1
SWAPB0
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
POLB3
POLB2
POLB1
POLB0
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
CICCENB3
CICCENB2
CICCENB1
CICCENB0
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CIPERENB
RAMPB[1:0]
WAVEGENB[2:0]
Access
R/W
R
R/W
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0