Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
842
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
32.6.11 DMA, Interrupts and Events
32.6.11.1 DMA Operation
The ADC generates the following DMA request:
z
Result Conversion Ready (RESRDY): the request is set when a conversion result is available and cleared when
the RESULT register is read. When the averaging operation is enabled, the DMA request is set when the
averaging is completed and result is available.
the RESULT register is read. When the averaging operation is enabled, the DMA request is set when the
averaging is completed and result is available.
32.6.11.2 Interrupts
The ADC has the following interrupt sources:
z
Result Conversion Ready: RESRDY. This is an asynchronous interrupt and can be used to wake-up the device
from any sleep mode.
from any sleep mode.
z
Overrun: OVERRUN
z
Window Monitor: WINMON. This is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
sleep mode.
z
Synchronization Ready: SYNCRDY. This is an asynchronous interrupt and can be used to wake-up the device
from any sleep mode.
from any sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag
is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the
corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or
one common interrupt request line for all the interrupt sources. This is device dependent.
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag
is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the
corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or
one common interrupt request line for all the interrupt sources. This is device dependent.
for details. If the peripheral has one common interrupt request
line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is
present.
present.
32.6.11.3 Events
The peripheral can generate the following output events:
z
Result Ready (RESRDY)
z
Window Monitor (WINMON)
Output events must be enabled to be generated. Writing a one to an Event Output bit in the Event Control register
(EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output
(EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output
Table 32-5. Module Request for ADC
Condition
Interrupt request
Event output
Event input
DMA request
DMA request is
cleared
Result Ready
x
x
x
When result
register is read
Overrun
x
Window Monitor
x
x
Synchronization
Ready
Ready
x
Start Conversion
x
ADC Flush
x