Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
861
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
32.8.10 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x16
Reset:
0x00
Property:
Write-Protected
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchroni-
zation Ready interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and the corresponding interrupt
request.
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchroni-
zation Ready interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and the corresponding interrupt
request.
z
Bit 2 – WINMON: Window Monitor Interrupt Enable
0: The window monitor interrupt is disabled.
1: The window monitor interrupt is enabled, and an interrupt request will be generated when the Window Monitor
interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Window Monitor Interrupt Enable bit and the corresponding interrupt request.
0: The window monitor interrupt is disabled.
1: The window monitor interrupt is enabled, and an interrupt request will be generated when the Window Monitor
interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Window Monitor Interrupt Enable bit and the corresponding interrupt request.
z
Bit 1 – OVERRUN: Overrun Interrupt Enable
0: The Overrun interrupt is disabled.
1: The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Interrupt Enable bit and the corresponding interrupt request.
0: The Overrun interrupt is disabled.
1: The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Interrupt Enable bit and the corresponding interrupt request.
z
Bit 0 – RESRDY: Result Ready Interrupt Enable
0: The Result Ready interrupt is disabled.
1: The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result Ready inter-
rupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Result Ready Interrupt Enable bit and the corresponding interrupt request.
0: The Result Ready interrupt is disabled.
1: The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result Ready inter-
rupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Result Ready Interrupt Enable bit and the corresponding interrupt request.
Bit
7
6
5
4
3
2
1
0
SYNCRDY
WINMON
OVERRUN
RESRDY
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0