Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
862
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
32.8.11 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name:
INTENSET
Offset:
0x17
Reset:
0x00
Property:
Write-Protected
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the Synchronization
Ready interrupt.
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the Synchronization
Ready interrupt.
z
Bit 2 – WINMON: Window Monitor Interrupt Enable
0: The Window Monitor interrupt is disabled.
1: The Window Monitor interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Window Monitor Interrupt bit and enable the Window Monitor interrupt.
0: The Window Monitor interrupt is disabled.
1: The Window Monitor interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Window Monitor Interrupt bit and enable the Window Monitor interrupt.
z
Bit 1 – OVERRUN: Overrun Interrupt Enable
0: The Overrun interrupt is disabled.
1: The Overrun interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Interrupt bit and enable the Overrun interrupt.
0: The Overrun interrupt is disabled.
1: The Overrun interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Interrupt bit and enable the Overrun interrupt.
z
Bit 0 – RESRDY: Result Ready Interrupt Enable
0: The Result Ready interrupt is disabled.
1: The Result Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Result Ready Interrupt bit and enable the Result Ready interrupt.
0: The Result Ready interrupt is disabled.
1: The Result Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Result Ready Interrupt bit and enable the Result Ready interrupt.
Bit
7
6
5
4
3
2
1
0
SYNCRDY
WINMON
OVERRUN
RESRDY
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0