Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Fiche De Données
Codes de produits
ATSAMD21-XPRO
942
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
Table 36-22. Single-Ended Mode
Notes: 1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage
range.
2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel com-
mon mode voltage) for all VIN:
z
VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
z
VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC perfor-
mance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power
supply.
supply.
36.9.4.1 Performance with the Averaging Digital Feature
Averaging is a feature which increases the sample accuracy. ADC automatically computes an average value of multiple
consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samples-to-be-
collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is available
in the Result register (RESULT).
consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samples-to-be-
collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is available
in the Result register (RESULT).
Table 36-23. Averaging feature
36.9.4.2 Performance with the hardware offset and gain correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is handled by the
Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register
Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ENOB
Effective Number of Bits
With gain compensation
-
9.5
9.8
Bits
TUE
Total Unadjusted Error
1x gain
-
10.5
14.0
LSB
INL
Integral Non-Linearity
1x gain
1.0
1.6
3.5
LSB
DNL
Differential Non-Linearity
1x gain
+/-0.5
+/-0.6
+/-0.95
LSB
Gain Error
Ext. Ref. 1x
-5.0
0.7
+5.0
mV
Gain Accuracy
Ext. Ref. 0.5x
+/-0.2
+/-0.34
+/-0.4
%
Ext. Ref. 2x to 16X
+/-0.01
+/-0.1
+/-0.2
%
Offset Error
Ext. Ref. 1x
-5.0
1.5
+5.0
mV
SFDR
Spurious Free Dynamic Range
1x Gain
F
F
CLK_ADC
= 2.1MHz
F
IN
= 40kHz
A
IN
= 95%FSR
63.1
65.0
67.0
dB
SINAD
Signal-to-Noise and Distortion
47.5
59.5
61.0
dB
SNR
Signal-to-Noise Ratio
48.0
60.0
64.0
dB
THD
Total Harmonic Distortion
-65.4
-63.0
-62.1
dB
Noise RMS
T = 25°C
-
1.0
-
mV
Average
Number
Conditions
SNR (dB)
SINAD (dB)
SFDR (dB)
ENOB
(bits)
1
In differential mode, 1x gain,
V
DDANA
=3.0V,
V
REF
=1.0V, 350kSps
66.0
65.0
72.8
9.75
8
67.6
65.8
75.1
10.62
32
69.7
67.1
75.3
10.85
128
70.4
67.5
75.5
10.91