Linear Technology LTC2364-18 with LTC6655-5/LT6202: 18-Bit, 250ksps, Pseudo-Differential Unipolar SAR ADC with 97dB SNR. Req DC718 or DC59 DC1813A-H Fiche De Données

Codes de produits

DC1813A-H

LT6202/LT6203/LT6204

620234fd

Amplifier Characteristics
Figure 1 shows a simplified schematic of the LT6202/

LT6203/LT6204, which has two input differential ampli-

fiers in parallel that are biased on simultaneously when

the common mode voltage is at least 1.5V from either

rail. This topology allows the input stage to swing from

the positive supply voltage to the negative supply voltage.

As the common mode voltage swings beyond V

– 1.5V,

current source I

saturates and current in Q1/Q4 is zero.

Feedback is maintained through the Q2/Q3 differential

amplifier, but with an input g

reduction of 1/2. A similar

effect occurs with I

when the common mode voltage

swings within 1.5V of the negative rail. The effect of the

reduction is a shift in the V

as I

or I

saturate.

APPLICATIONS INFORMATION

Input bias current normally flows out of the + and – inputs.

The magnitude of this current increases when the input

common mode voltage is within 1.5V of the negative rail,

and only Q1/Q4 are active. The polarity of this current

reverses when the input common mode voltage is within

1.5V of the positive rail and only Q2/Q3 are active.
The second stage is a folded cascode and current mir-

ror that converts the input stage differential signals to a

single ended output. Capacitor C1 reduces the unity cross

frequency and improves the frequency stability with-

out degrading the gain bandwidth of the amplifier. The

differential drive generator supplies current to the output

transistors that swing from rail-to-rail.

DIFFERENTIAL

DRIVE

GENERATOR

–

Q10

Q11

DESD2

DESD4

DESD3

DESD1

DESD5

DESD6

–

BIAS

–V

V–

6203/04 F01

Figure 1. Simplified Schematic