Linear Technology DC1337A - LTC2309: 12-bit, 8-channel SAR ADC with I²C I/F, req DC590 DC1337A DC1337A Fiche De Données

LTC2309

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AppLICAtIOns InFORMAtIOn

Overview
The LTC2309 is a low noise, 8-channel, 12-bit succes-

sive approximation register (SAR) A/D converter with an

I

2

C compatible serial interface. The LTC2309 includes a

precision internal reference and a configurable 8-chan-

nel analog input multiplexer (MUX). The ADC may be

configured to accept single-ended or differential signals

and can operate in either unipolar or bipolar mode. A

sleep mode option is also provided to further reduce

power during inactive periods.
The  LTC2309  communicates  through  a  2-wire  I

2

C

compatible serial interface. Conversions are initiated

by signaling a STOP condition after the part has been

successfully addressed for a read/write operation. The

device will not acknowledge (NACK) an external request

until the conversion is finished. After a conversion is

finished,  the  device  is  ready  to  accept  a  read/write

request.  Once  the  LTC2309  is  addressed  for  a  read

operation,  the  device  begins  outputting  the  conver-

sion result under the control of the serial clock (SCL).

There is no latency in the conversion result. There are

12 bits of output data followed by 4 trailing zeros. Data

is updated on the falling edges of SCL, allowing the

user to reliably latch data on the rising edge of SCL. A

write operation may follow the read operation by using

a repeat START or a STOP condition may be given to

start a new conversion. By selecting a write operation,

the ADC can be programmed with a 6-bit D

IN

word. The

D

IN

word configures the MUX and programs various

modes of operation of the ADC.
During  a  conversion,  the  internal  12-bit  capacitive

charge redistribution DAC output is sequenced through

a successive approximation algorithm by the SAR start-

ing from the most significant bit (MSB) to the least

significant bit (LSB). The sampled input is successively

compared with binary weighted charges supplied by

the capacitive DAC using a differential comparator. At

the end of a conversion, the DAC output balances the

analog input. The SAR contents (a 12-bit data word)

that represent the sampled analog input are loaded into

12 output latches that allow the data to be shifted out

via the I

2

C interface.

Programming the LTC2309
The various modes of operation of the LTC2309 are

programmed by a 6-bit D

IN

word. The SDI input data

bits are loaded on the rising edge of SCL during a write

operation, with the S/D bit loaded on the first rising edge

and the SLP bit on the sixth rising edge (see Figure 8b

in the I

2

C Interface section). The input data word is

defined as follows:

S/D O/S S1 S0 UNI SLP

 S/D = SINGLE-ENDED/DIFFERENTIAL BIT
 O/S = ODD/SIGN BIT
 S1 = CHANNEL SELECT BIT 1
 S0 = CHANNEL SELECT BIT 0
 UNI = UNIPOLAR/BIPOLAR BIT
 SLP = SLEEP MODE BIT

Analog Input Multiplexer
The  analog  input  MUX  is  programmed  by  the  S/D,

O/S, S1 and S0 bits of the D

IN

word. Table 1 lists the

MUX configurations for all combinations of the con-

figuration bits. Figure 1a shows several possible MUX

configurations and Figure 1b shows how the MUX can

be reconfigured from one conversion to the next.

Driving the Analog Inputs
The analog inputs of the LTC2309 are easy to drive.

Each of the analog inputs can be used as a single-ended

input relative to the COM pin (CH0-COM, CH1-COM,

etc.) or in differential input pairs (CH0 and CH1, CH2

and CH3, CH4 and CH5, CH6 and CH7). Figure 2 shows

how to drive COM for single-ended inputs in unipolar

and bipolar modes. Regardless of the MUX configura-

tion, the “+” and “–” inputs are sampled at the same

instant. Any unwanted signal that is common to both

inputs will be reduced by the common mode rejection

of the sample-and-hold circuit. The inputs draw only

one small current spike while charging the sample-and-

hold capacitors during the acquire mode. In conversion