On Semiconductor NCP5030 Evaluation Board NCP5030MTTXGEVB NCP5030MTTXGEVB NCP5030MTTXGEVB Fiche De Données

from the supply according to the application’s specific
requirements. The I

peak

 maximum value is 4 A, resulting

in a minimum resistor value of 30 k

W. Please refer to

Figure 8 I

PEAK_MAX

 Vs R

PCA

 page 6 to choose R

PCA

value versus I

PEAK_MAX

. By limiting the peak current to

the needs of the application, the inductor sizing can be
scaled appropriately to the specific requirements. This
allows the PCB footprint to be minimized.

C

OUT

 stores energy during the T

OFF

 phase and sustains

the load current during the T

ON

 phase. In order ensure the

loop stability and minimize the output ripple, at least 22 

mF

low ESR multi−layer ceramic capacitor type X5R is
recommended.

The V

IN

 and PV

IN

 input pin need to be bypassed by a

X5R or an equivalent low ESR ceramic capacitor. Near the
PV

IN

 pin at least 10 

mF 6.3 V or higher ceramic capacitor

is needed. Regarding V

IN

 pin a 1 

mF 6.3 V close to the pad

is sufficient. Some recommended capacitors include but
are not limited to:
22 

mF 6.3 V 0805

TDK: C2012X5R0J226MTJ

22 

mF 6.3 V 1206

MURATA: GRM31CR60J226KE19L

10 

mF 6.3 V 0805

TDK C2012X5R0J106MT

The NCP5030 regulates the load current. If there is an

open load condition such as a lost connection to the White
LED, the converter keeps supplying current to the Cout
capacitor causing the output voltage to rise rapidly. To
prevent the device from being damaged and to eliminate
external protection components such as zener diode, the
NCP5030 incorporates an OVP circuit, which monitors the
output voltage with a resistive divider network and a
comparator and voltage reference. If the output reaches 6 V
(nominal), the OVP circuit will detect a fault and inhibit
PWM operation. This comparator has 200 mV hysteresis to
allow the PWM operation to resume automatically when
the load is reconnected and when the voltage drops below
5.8 V.

To ensure proper operation under low input voltage

conditions, the device has a built−in Under−Voltage Lock
Out (UVLO) circuit. The device remains disabled until the
input voltage exceeds 2.35 V (nominal). This circuit has
100 mV hysteresis to provide noise immunity to transient
conditions.

Normal operation of the NCP5030 is disabled to protect

the device if the junction temperature exceeds 160

°C.

When the junction temperature drops below 140

°C, normal

operation will resume.

As with all switching DC/DC converter, care must be

observed to the PCB board layout and component
placement. To prevent electromagnetic interference (EMI)
problems and reduce voltage ripple of the device any
copper trace, which see high frequency switching path,
should be optimized. So the input and output bypass
ceramic capacitor, C

IN

 and C

OUT

 as depicted in Figure 24

must be placed as close as possible the NCP5030 and
connected directly between pins and ground plane. In
additional, the track connection between the inductor and
the switching input, SW pin must be minimized to reduce
EMI radiation.

TBD