Mikroelektronika MIKROE-442 Fiche De Données
mikroBasic PRO for dsPIC30/33 and PIC24
MikroElektronika
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Interrupts
The dsPIC30/33 and PIC24 interrupt controller module reduces numerous peripheral interrupt request signals to a
single interrupt request signal to the dsPIC30/33 and PIC24 CPU and has the following features:
- Up to 8 processor exceptions and software traps
- 7 user-selectable priority levels
- Interrupt Vector Table (IVT) with up to 62 vectors (dsPIC30) or up to 118 vectors (dsPIC33 and PIC24)
- A unique vector for each interrupt or exception source
- Fixed priority within a specified user priority level
- Alternate Interrupt Vector Table (AIVT) for debug support
ISRs are organized in IVT. ISR is defined as a standard function but with the iv directive afterwards which connects the
function with specific interrupt vector. For example
iv IVT_ADDR_T1INTERRUPT
is IVT address of Timer1 interrupt
source of the dsPIC 30F3014 MCU. For more information on IVT refer to the dsPIC30/33 and PIC24 Family Reference
Manual.
Function Calls from Interrupt
Calling functions from within the interrupt routine is possible. The compiler takes care about the registers being used,
both in “interrupt” and in “main” thread, and performs “smart” context-switching between two of them, saving only the
registers that have been used in both threads. It is not recommended to use a function call from interrupt. In case of
doing that take care of stack depth.
Use the DisableContextSaving to instruct the compiler not to automatically perform context-switching. This means that
no register will be saved/restored by the compiler on entrance/exit from interrupt service routine.
This enables the user to manually write code for saving registers upon entrance and to restore them before exit from
interrupt.
Interrupt Handling
For the sake of interrupt handling convenience, new keyword,
iv
, is introduced. It is used to declare Interrupt Vector
Table (IVT) address for a defined interrupt routine:
sub procedure int1() iv IVT_ADDR_U1RXINTERRUPT
asm
nop
end asm
end sub
Now it is possible to explicitly declare interrupt routine address:
sub procedure int1() org 0x600 iv IVT_ADDR_U1RXINTERRUPT
asm
nop
end asm
end sub