STMicroelectronics 250W TRANSITION-MODE PFC PRE-REGULATOR WITH L6563S EVL6563S-250W EVL6563S-250W Fiche De Données
Codes de produits
EVL6563S-250W
AN3119
Main characteristics and circuit description
Doc ID 16849 Rev 2
5/32
the mains voltage. Additionally, pin #10 (RUN) is connected to pin# 5 (V
FF
) through the R27
and R28 resistor divider, providing a voltage level for brown-out (AC mains under voltage)
protection. A voltage on the RUN pin below 0.8 V shuts down (not latched) the IC and brings
its consumption to a considerably lower level. The L6563S restarts as the voltage at the pin
rises above 0.88 V.
protection. A voltage on the RUN pin below 0.8 V shuts down (not latched) the IC and brings
its consumption to a considerably lower level. The L6563S restarts as the voltage at the pin
rises above 0.88 V.
The R21, R25, R26 and R33 dividers provide the information regarding the output voltage
level to the L6563S pin #7 (PFC_OK). It is required by the L6563S output voltage monitoring
and disable functions used for PFC protection purposes.
level to the L6563S pin #7 (PFC_OK). It is required by the L6563S output voltage monitoring
and disable functions used for PFC protection purposes.
If the voltage on pin #7 exceeds 2.5 V the IC stops switching and restarts as the voltage on
the pin falls below 2.4 V, realizing the so-called dynamic OVP, preventing the output voltage
becoming excessive in case of transient, due to the slow response of the error amplifier.
However, if contemporaneously the voltage of the INV pin falls below 1.66 V (typ.), a
feedback failure is assumed. In this case the device is latched off. Normal operation can be
resumed only by cycling Vcc, bringing its value lower than 6 V, before moving up to turn-on
the threshold.
the pin falls below 2.4 V, realizing the so-called dynamic OVP, preventing the output voltage
becoming excessive in case of transient, due to the slow response of the error amplifier.
However, if contemporaneously the voltage of the INV pin falls below 1.66 V (typ.), a
feedback failure is assumed. In this case the device is latched off. Normal operation can be
resumed only by cycling Vcc, bringing its value lower than 6 V, before moving up to turn-on
the threshold.
Additionally, if the voltage on pin #7 (PFC_OK) is tied below 0.23 V, the L6563S is shut
down. To restart the L6563S operation the voltage on pin #7 (PFC_OK) must increase
above 0.27 V. This function can be used as a remote on/off control input.
down. To restart the L6563S operation the voltage on pin #7 (PFC_OK) must increase
above 0.27 V. This function can be used as a remote on/off control input.
To allow the interfacing of the board with a D2D converter the J3 connector allows the
powering of the L6563S with an external Vcc. It also gives the opportunity to manage failure
or abnormal conditions via the PWM_LATCH (#8) and PWM_STOP (#9) pins. The L6563S
operation can also be disabled or enabled to properly manage light load or failure conditions
by the D2D via the PFC_OK pin (#7), still available at pin #5 of J3 (on/off). For further details
please see
powering of the L6563S with an external Vcc. It also gives the opportunity to manage failure
or abnormal conditions via the PWM_LATCH (#8) and PWM_STOP (#9) pins. The L6563S
operation can also be disabled or enabled to properly manage light load or failure conditions
by the D2D via the PFC_OK pin (#7), still available at pin #5 of J3 (on/off). For further details
please see
.