STMicroelectronics Discovery kit for STM32F401 line - with STM32F401VC MCU STM32F401C-DISCO STM32F401C-DISCO Fiche De Données
Codes de produits
STM32F401C-DISCO
6
HigH‑perFomance
art accelerator performance
Unleashing the full performance of the core beyond the embedded Flash’s intrinsic speed is an art. Combined with ST’s 90 nm technology, our
ART Accelerator™ achieves a linear performance up to 180 MHz, offering 225 DMIPS and 608 CoreMark performance executing from Flash.
The acceleration mechanism is made possible using a prefetch queue, a branch cache and a smart arbitration mechanism.
ART Accelerator™ achieves a linear performance up to 180 MHz, offering 225 DMIPS and 608 CoreMark performance executing from Flash.
The acceleration mechanism is made possible using a prefetch queue, a branch cache and a smart arbitration mechanism.
•
MCUs using less advanced accelerators or
slower embedded Flash memories impact
execution performance as wait states
occur.
slower embedded Flash memories impact
execution performance as wait states
occur.
•
MCUs using faster Flash but no branch
cache acceleration to achieve performance
usually show higher power consumption
as a result of more accesses to a
power‑hungry Flash.
cache acceleration to achieve performance
usually show higher power consumption
as a result of more accesses to a
power‑hungry Flash.
CPU frequency
CoreMark score
608
566
180 MHz
168 MHz
84 MHz
Linear execution performance from Flash
STM32F407
STM32F401
285
STM32F429
richer graphic and animations with st chrom‑art accelerator
In applications using a display, graphical data generation can consume a lot of CPU bandwidth. To offload the CPU, a dedicated DMA has
been developed by ST to perform graphic content copy from the frame buffer (internal or external RAM) to the display interface (FMC or TFT
controller). This advanced graphic accelerator, the Chrom‑ART Accelerator, achieves a twofold increase in performance versus the CPU.
In addition to raw data copy, additional functionalities are supported such as image format conversion or image blending (image mixing with
some transparency).
been developed by ST to perform graphic content copy from the frame buffer (internal or external RAM) to the display interface (FMC or TFT
controller). This advanced graphic accelerator, the Chrom‑ART Accelerator, achieves a twofold increase in performance versus the CPU.
In addition to raw data copy, additional functionalities are supported such as image format conversion or image blending (image mixing with
some transparency).
Human machine interface implementation
example
example
•
STM32F427/429 using Chrom‑ART
Accelerator, internal or external memory for
frame buffer and TFT controller for display
Accelerator, internal or external memory for
frame buffer and TFT controller for display
•
Up to VGA/SVGA
•
16‑/32‑bit external memory interface
•
Recommended packages: LQFP100,
LQFP144, LQFP176/BGA176 or
LQFP208/BGA216
LQFP144, LQFP176/BGA176 or
LQFP208/BGA216
Bus matrix
Cortex-M4
Internal
Flash up
to 2 Mbytes
Internal
SRAM
256 Kbytes
External
memory
memory
controller
Chrom-ART
Accelerator
TFT
Controller
Dedicated TFT interface with
fully programmable panel
timings
LCD TFT
display or
chip-on-glass
display connected to the
parallel interface
Or
Dedicated interface (up to
32-bit/90 MHz) with
Flash, SRAM and
SDRAM support
16/32-bit
BRSTM32F40113.indd 6
29-Aug-13 16:44:38