STMicroelectronics FlexSPIN: SPI configurable stepper and DC multi motor driver evaluation board EVAL6460 EVAL6460 Fiche De Données

Doc ID 17713 Rev 1

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L6460 can communicate with an external microprocessor by using an integrated slave SPI 
(serial protocol interface). Through this interface almost all L6460 functionalities can be 
controlled and all the ICs can be seen as a register map made by 128 register of 16-bit 
each.

The SPI is a simple industry standard communications interface commonly used in 
embedded systems and it has the following four I/O pins:

–

MISO (master input slave output)

–

MOSI (master output slave input)

–

SCLK (serial clock [controlled by the master])

–

nSS (slave select active low [controlled by the master])

The “MISO” (master in, slave out) signal carries synchronous data from the slave to the 
master device. The MOSI (master out, slave in) signal carries synchronous data from the 
master to the slave device. The SCLK signal is driven by the master, synchronizing all data 
transfers. Each SPI slave device has one nSS signal that is an active-low slave input/master 
output pin. Slave devices do not respond to transactions unless their nSS input signal is 
driven low. Master device interfacing with multiple SPI slave devices has an nSS signal for 
each slave device.

L6460 will maintain its MISO pin in high impedance until it does not recognize its address in 
serial frame.

A read transaction (see 

) is always started by the master device that lowers the 

nSS pin. The other bits are then sent on the MOSI pin with this order:

1.

7-bit representing the address of the register that must be read (MSB first [A

6

…A

0

]);

2. 

2-bit that must be “10” for a read transaction;

3. 

2-bit representing L6460 IC address;

4. 

1-bit reserved for future use that must be set at “0”.

At this point the data stored in the register at the selected address will be shifted out on the 
MISO pin.

The read operation is terminated by raising the signal on nSS pin.