STMicroelectronics Double output SMPS for power line application using ALTAIR04-900 primary controller EVLALTAIR900-M1 EVLALTAIR900-M1 Fiche De Données

Codes de produits
EVLALTAIR900-M1
Page de 29
Application information
ALTAIR04-900
14/29
Doc ID 18211 Rev 2
The voltage on the pin is both top and bottom limited by a double clamp, as illustrated in the 
internal diagram of the ZCD block of 
. The upper clamp is typically at 3.3 V, while 
the lower clamp is located at -60mV. The interface between the pin and the auxiliary winding 
is a resistor divider. Its resistance ratio as well as the individual resistance values has to be 
properly chosen (see “
” and “
Please note that the maximum I
ZCD/FB
 sunk/sourced current has to not exceed ±2 mA 
(AMR) in all the Vin range conditions. No capacitor is allowed between ZCD pin and the 
auxiliary transformer.
The switching frequency is top-limited below 166 kHz, as the converter’s operating 
frequency tends to increase excessively at light load and high input voltage.
A Starter block is also used to start-up the system, that is, to turn on the MOSFET during 
converter power-up, when no or a too small signal is available on the ZCD pin.
The starter frequency is 2 kHz if COMP pin below burst mode threshold, i.e. 1 V, while it 
becomes 8 kHz if this voltage exceed this value.
After the first few cycles initiated by the starter, as the voltage developed across the auxiliary 
winding becomes large enough to arm the ZCD circuit, MOSFET’s turn-on starts to be 
locked to transformer demagnetization, hence setting up QR operation.
The starter is activated also when the IC is in CC regulation and the output voltage is not 
high enough to allow the ZCD triggering.
If the demagnetization completes – hence a negative-going edge appears on the ZCD pin – 
after a time exceeding time T
BLANK
 from the previous turn-on, the MOSFET is turned on 
again, with some delay to ensure minimum voltage at turn-on. If, instead, the negative-going 
edge appears before T
BLANK
 has elapsed, it is ignored and only the first negative-going 
edge after T
BLANK
 turns-on the MOSFET. In this way one or more drain ringing cycles is 
skipped (“valley-skipping mode”, 
) and the switching frequency is prevented from 
exceeding 1/T
BLANK
.
Figure 12.
Drain ringing cycle skipping as the load is progressively reduced
Note that when the system operates in valley skipping-mode, uneven switching cycles may 
be observed under some line/load conditions, due to the fact that the OFF-time of the 
MOSFET is allowed to change with discrete steps of one ringing cycle, while the OFF-time 
needed for cycle-by-cycle energy balance may fall in between. Thus one or more longer 
switching cycles is compensated by one or more shorter cycles and vice versa. However, 
this mechanism is absolutely normal and there is no appreciable effect on the performance 
of the converter or on its output voltage. 
 
P
in
= P
in'
(limit condition)
P
in
= P
in''
< P
in'
P
in
= P
in'''
< P
in''
t
V
DS
 T
FW 
 T
osc 
 T
 T
ON 
t
V
DS
 T
osc 
t
V
DS
 T
osc