Intel III Xeon 900 MHz 80526KY9002M Fiche De Données
Codes de produits
80526KY9002M
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
INTEGRATION TOOLS
79
The DBRESET# output signal from the ITP is an open drain with about 5 ohms of RDS. The usual
implementation is to connect it to the PWROK open drain signal on the PCIset components as an OR input to
initiate a system reset. In order for the DBRESET# signal to work properly, it must actually reset the entire
target system. The signal should be pulled up (Intel recommends a 240 ohm resistor, but system designers
will need to fine tune specific system designs) to meet two considerations: (1) the signal must be able to meet
VIL of the system, and (2) it must allow the signal to meet the specified rise time. When asserted by the ITP,
the DBRESET# signal will remain asserted for 100 mS. A large capacitance should not be present on this
signal as it may prevent a full charge from building up within 100 mS.
implementation is to connect it to the PWROK open drain signal on the PCIset components as an OR input to
initiate a system reset. In order for the DBRESET# signal to work properly, it must actually reset the entire
target system. The signal should be pulled up (Intel recommends a 240 ohm resistor, but system designers
will need to fine tune specific system designs) to meet two considerations: (1) the signal must be able to meet
VIL of the system, and (2) it must allow the signal to meet the specified rise time. When asserted by the ITP,
the DBRESET# signal will remain asserted for 100 mS. A large capacitance should not be present on this
signal as it may prevent a full charge from building up within 100 mS.
8.1.6.3 Signal Note: TDO and TDI
The TDO signal of each processor has a 2.5V Tolerant open-drain driver. The TDI signal of each
processor contains a 150-ohm
processor contains a 150-ohm
pull-up to VCC
TAP
. When connecting one Pentium III Xeon processor at
600 MHz+ to the next, or connecting to the TDI of the first processor, no external pull-up is required.
However, the last processor of the chain does require a 150-ohm pull-up resistor to VCC
However, the last processor of the chain does require a 150-ohm pull-up resistor to VCC
TAP
at TDO before
passing the TAP signal to the next device in the chain.
8.1.6.4 Signal Note: TCK and TMS
WARNING
A significant number of target systems have had signal integrity issues with the TCK signal. TCK
is a critical clock signal and must be routed accordingly; make sure to observe power and ground
plane integrity for this signal. Follow the guidelines below and assure the quality of the signal
when beginning use of an ITP to debug your target.
is a critical clock signal and must be routed accordingly; make sure to observe power and ground
plane integrity for this signal. Follow the guidelines below and assure the quality of the signal
when beginning use of an ITP to debug your target.
Due to the number of loads on the TCK signal, special care should be taken when routing this. Poor routing
can lead to multiple clocking of some agents on the debug chain, usually on the falling edge of TCK. This
causes information to be lost through the chain and can result in bad commands being issued to some agents
on the chain. Systems using other TCK routing schemes, particularly those with ‘T' or ‘Y' configurations where
the trace from the source to the ‘T' is long, could have signal integrity problems.
can lead to multiple clocking of some agents on the debug chain, usually on the falling edge of TCK. This
causes information to be lost through the chain and can result in bad commands being issued to some agents
on the chain. Systems using other TCK routing schemes, particularly those with ‘T' or ‘Y' configurations where
the trace from the source to the ‘T' is long, could have signal integrity problems.
The suggested routing scheme is to drive each of the agent TCK signals individually from a buffer device.
Figure 31 shows how the TCK signal should be routed to the agents in a 2-way Pentium® III Xeon™
processor at 600 MHz+ system incorporating the Intel® 840 PCIset. A Bessel filter is recommended over a
series termination at the output of each buffer. The values shown in Figure 31 are only examples. The
designer should determine the LC values appropriate for their particular application.
Figure 31 shows how the TCK signal should be routed to the agents in a 2-way Pentium® III Xeon™
processor at 600 MHz+ system incorporating the Intel® 840 PCIset. A Bessel filter is recommended over a
series termination at the output of each buffer. The values shown in Figure 31 are only examples. The
designer should determine the LC values appropriate for their particular application.
If it is desired to ship production systems without the 2.5V buffers installed, then pull-up resistors
should be placed at the outputs to prevent TCK from floating.
should be placed at the outputs to prevent TCK from floating.