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 Specification 

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stores (referred to as “fast strings”) for optimal performance. FXSAVE may also be 

internally implemented using write combining stores. Due to this erratum, stores of a 

WB (write back) memory type to a cache line previously written by a preceding fast 

string/FXSAVE instruction may be observed before string/FXSAVE stores. 

Implication:  A write-back store may be observed before a previous string or FXSAVE related store. 

Intel has not observed this erratum with any commercially available software. 

Workaround:  Software desiring strict ordering of string/FXSAVE operations relative to subsequent 

write-back stores should add an MFENCE or SFENCE instruction between the 

string/FXSAVE operation and following store-order sensitive code such as that used for 

synchronization. 

For the steppings affected, see the 

Summary Tables of Changes. 

 

During the transition from real mode to protected mode, if an SMI (System 

Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection 

Enable, bit 0) and the first far JMP, the subsequent RSM (Resume from 

System Management Mode) may cause the lower two bits of CS segment register to 

be corrupted. 

Implication:  The corruption of the bottom two bits of the CS segment register will have no impact 

unless software explicitly examines the CS segment register between enabling 

protected mode and the first far JMP. Intel® 64 and IA-32 Architectures Software 

Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section 

titled "Switching to Protected Mode" recommends the far JMP immediately follows the 

write to CR0 to enable protected mode. Intel has not observed this erratum with any 

commercially available software. 

Workaround: None Identified. 

For the steppings affected, see the 

Summary Tables of Changes

 

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