Intel III M 866 MHz BXM80530B866512 Fiche De Données
Codes de produits
BXM80530B866512
Mobile Intel
®
Pentium
®
III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,
900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage
700 MHz, Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz
283653-002 Datasheet
23
Table 7. Recommended Resistors for Mobile Pentium III Processor Signals
Recommended
Resistor Value (
Ω
Ω
Ω
Ω
)
Mobile Pentium III Processor Signal
1, 2
No pull-up
GHI#
3
10 pull-down
BREQ0#
4
56.2 pull-up
RESET#
5
150 pull-up
PICD[1:0], TDI, TDO
270 pull-up
SMI#
680 pull-up
STPCLK#
1K pull-up
INIT#, TCK, TMS
1K pull-down
TRST#
1.5K pull-up
A20M#, FERR#, FLUSH#, IERR#, IGNNE#, LINT0/INTR,
LINT1/NMI, PREQ#, PWRGOOD, SLP#
LINT1/NMI, PREQ#, PWRGOOD, SLP#
NOTES:
1.
The recommendations above are only for signals that are being used. These recommendations are
maximum values only; stronger pull-ups may be used. Pull-ups for the signals driven by the chipset should
not violate the chipset specification. Refer to Section 3.1.4 for the required pull-up or pull-down resistors for
signals that are not being used.
maximum values only; stronger pull-ups may be used. Pull-ups for the signals driven by the chipset should
not violate the chipset specification. Refer to Section 3.1.4 for the required pull-up or pull-down resistors for
signals that are not being used.
2.
Open-drain signals must never violate the undershoot specification in Section 4.3. Use stronger pull-ups if
there is too much undershoot.
there is too much undershoot.
3.
GHI# has an on-die pull-up to V
CCT
.
4.
A pull-down on BREQ0# is an alternative to having the central agent to drive BREQ0# low at reset.
5.
A 56.2
Ω
1% terminating resistor connected to V
CCT
is required.
3.1.1 Power
Sequencing
Requirements
The mobile Pentium III processor has no power sequencing requirements. Intel recommends that
all of the processor power planes rise to their specified values within one second of each other.
The V
all of the processor power planes rise to their specified values within one second of each other.
The V
CC
power plane must not rise too fast. At least 200
µ
sec (T
R
) must pass from the time that
V
CC
is at 10% of its nominal value until the time that V
CC
is at 90% of its nominal value (see
Figure 4. Vcc Ramp Rate Requirement
Vcc
Volts
90% Vcc (nominal)
10% Vcc (nominal)
T
R
Time
3.1.2
Test Access Port (TAP) Connection
The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the
voltage levels supported by the TAP interface, Intel recommends that the mobile Pentium III
processor and the other 1.5-V JTAG specification compliant devices be last in the JTAG chain
voltage levels supported by the TAP interface, Intel recommends that the mobile Pentium III
processor and the other 1.5-V JTAG specification compliant devices be last in the JTAG chain