Intel C2338 FH8065501516761 Fiche De Données
Codes de produits
FH8065501516761
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
97
Volume 2—System Agent and Root Complex—C2000 Product Family
Global Error Reporting
9. The software has the following options for clearing the error status registers:
a. Read the Global and Local Log registers to identify the source of the error. Clear
the local error bits; this does not cause a generation of an interrupt with the
global bit still set. Then, clear the global error bit and write to the local error
register again with all 0s. Writing 0s to the local status does not clear any status
bit, but causes the re-evaluation of the error status bits. An error is reported if
any local error bit is unclear.
b. Read the Global and Local Log registers to identify the source of the error and
mask the error reporting for the error severity. Clear the system event and
global error status bits
—
this causes setting of the system event status bit if the
other global bits are still set. Then, clear the local error status bits
—
this causes
setting of the global error status bit if other local error bits are still set. Then,
unmask the system event to cause the SoC to report the error.
10. FERR logs the information of the first error detected by the associated error status
register (local or global). The FERR log remains unchanged until all bits in the
respective error status register are cleared by the software. When all error bits are
cleared, the FERR logging is re-enabled.
4.7.7.6
Error Counters
This feature allows the system management controller to monitor the component
health by periodically reporting the correctable error count. The error RAS structure
already provides a first-error status and a second-error status. Because the response
time of system management is on the order of milliseconds, reading and clearing the
error logs in time to detect short bursts of errors across the SoC component does not
happen. Over a long period of time, the software uses these values to monitor the rate
of change in the error occurrences. This helps identify potential component
degradations, especially with respect to the memory interface.
A register with one-hot encoding selects which error types participate in error counting.
More than one error is unlikely to occur within a cluster at a given time. The SoC only
counts one occurrence in one clock cycle. The selection register logically ORs-together
all of the selected error types to form a single count enable. This means that only one
counter increment occurs for one or all types selected. Register attributes are set to
write a 1 to clear.
Each cluster has one set of error counter/control registers.
• The SMBus device contains one 7-bit counter (SMBus_ERRCNT[6:0]).
— Bit[7] is an overflow bit, all bits are sticky with a write logic 1 to clear.
• The root complex device contains one 7-bit counter (RTF_ERRCNT[6:0]).
— Bit[7] is an overflow bit, all bits are sticky with a write logic 1 to clear.
• The internal memory controller contains one 7-bit counter (Dunit_ERRCNT[6:0]).
— Bit[7] is an overflow bit, all bits are sticky with a write logic 1 to clear.
• The SoC system agent contains one 7-bit counter (Bunit_ERRCNT[6:0]).
— Bit[7] is an overflow bit, all bits are sticky with a write logic 1 to clear.