Intel C2550 FH8065401488912 Fiche De Données

Intel

Codes de produits

FH8065401488912

Volume 2—Interrupt Architecture—C2000 Product Family

Device Interrupt-Generating Capabilities

Intel

®

Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

124

Order Number: 330061-002US

For some events, either an SCI or an SMI is generated. This is determined by the SCI

Enable (SCI_EN) bit of the Power Management 1 Control (PM1_CNT) register. PM1_CNT

is a 32-bit register located in the I/O space at ACPI_BASE_ADDRESS (ABASE) + 4.

Whether an SMI is generated, an SMI is controlled by the Global SMI Enable

(GBL_SMI_EN) bit of the SMI Control and Enable (SMI_EN) register. SMI_EN is a 32-bit

register located in the I/O space at ACPI_BASE_ADDRESS (ABASE) + 30h. The 32-bit

SMI Status (SMI_STS) register is located in the I/O space at ACPI_BASE_ADDRESS

§ §

Table 6-6.

Device SCI, NMI, and SMI Generating Capabilities

Device

SCI

NMI

SMI

Root Complex Event

Collector (RCEC)

X

X

Root Ports

X

X

SATA2 and SATA3

USB 2.0

X

GbE

SMBus

iLB Legacy

Refer to

“Intel Legacy Block (iLB)

X

X

UART

Power Management

X

X