Intel C2518 FH8065501516710 Fiche De Données

Intel

Codes de produits

FH8065501516710

Volume 2—UART Controller—C2000 Product Family

UART Operation

Intel

®

Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

462

Order Number: 330061-002US

20.4.1.2

FIFO Polled Mode Operation

With the FIFOs enabled (FIFO Control Register, bit 0 = 1b), setting Interrupt Enable

Register (IER), bits [3:0] = 000b, puts the serial port in the FIFO polled mode of

operation. Since the receiver and the transmitter are controlled separately, either one

or both are in the polled mode of operation. In this mode, the software checks the

receiver and transmitter status through the Line Status Register (LSR). As stated in the

register description:

• LSR[0] is set as long as 1 byte is in the receiver FIFO.
• LSR[1] through LSR[4] specify which error(s) has occurred for the character at the

top of the FIFO. The character error status is handled the same way as the

interrupt mode. The Interrupt Identification Register is not affected since

• LSR[5] indicates when the transmitter FIFO needs data.
• LSR[6] indicates that both the transmitter FIFO and shift register are empty.
• LSR[7] indicates whether any errors are in the receiver FIFO.