Intel E3845 FH8065301487715 Fiche De Données
Codes de produits
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
421
14.9.3
RID_CC—Offset 8h
Revision Identification and Class code registerSOXi Context Save/Restore: Yes
Access Method
Default: 03000000h
18:16
000b
RO
RSVD (RSVD_9):
Reserved
15:11
00h
RO
RSVD (RSVD_0):
Reserved
10
0b
RW
INTERRUPT_DISABLE (INTERRUPT_DISABLE_1):
ID: 0= Interrupt message
enabled, 1= disabled
9:3
00h
RO
RSVD (RSVD_2):
Reserved
2
0b
RW
BUS_MASTER_ENABLE (BUS_MASTER_ENABLE_3):
BME: 0= Blocks the sending of
MSI interrupts, 1= permits
1
0b
RW
MEMORY_SPACE_ENABLE (MEMORY_SPACE_ENABLE_4):
MSE: 0= Memory space
disabled, 1= enabled
0
0b
RW
IO_SPACE_ENABLE (IO_SPACE_ENABLE_5):
IOSE: 0= I/O space is disabled,
1=enabled
Bit
Range
Default &
Access
Description
Type:
PCI Configuration Register
(Size: 32 bits)
RID_CC:
Power Well:
Core
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BASE
_C
LAS
S
_CODE
_
1
SU
B_CLA
S
S_C
O
DE
_2
PROGRAMMING
_INTERF
A
C
E
_3
REVIS
ION_ID_0
Bit
Range
Default &
Access
Description
31:24
00000011b
RO
BASE_CLASS_CODE (BASE_CLASS_CODE_1):
BCC: MGGC0[VAMEN]=0, 03h else
04h
23:16
00000000b
RO
SUB_CLASS_CODE (SUB_CLASS_CODE_2):
MGGC0[VAMEN]= 1, 80h,
MGGC0[VAMEN]=0,determined based on GGC register, GMS and IVD
15:8
00h
RO
PROGRAMMING_INTERFACE (PROGRAMMING_INTERFACE_3):
MGGC0[VAMEN]= 0, 00h display controller, =1, 00h NOP