Intel E3845 FH8065301487715 Fiche De Données

Intel

®

 Atom™ Processor E3800 Product Family

4522

Datasheet

b. Drawback:

Clock delay compensation is less effective at compensating for mainboard delay

c. Soft Strap & Register Requirements:

Soft Strap LPCCLK_SLC = 0b

Configuration is reflected by register bit LPCC.LPCCLK_SLC=0b

Soft Strap LPCCLK1_ENB = 0b (ILB_LPC_CLK[1] disabled)  or 1b (ILB_LPC_CLK[1] 
enabled)  

2. Configuration is reflected by register bit LPCC.LPCCLK1EN=0b (ILB_LPC_CLK[1] 

disabled)  or 1b (ILB_LPC_CLK[1] enabled)  

3. On the main board: In this configuration, ILB_LPC_CLK[0] is looped back to 

ILB_LPC_CLK[1] on the main board. 

a. Benefit: 

Clock delay compensation in more effective at compensating for main board delay

b. Drawback:

Only ILB_LPC_CLK[0] is available for system clocking. ILB_LPC_CLK[1] must be 
disabled.

c. Soft Strap & Register Requirements:

Soft Strap LPCCLK_SLC = 1b

Configuration is reflected by register bit LPCC.LPCCLK_SLC=1b

Soft Strap LPCCLK1_ENB = 0b (ILB_LPC_CLK[1] disabled)    

Configuration is reflected by register bit LPCC.LPCCLK1EN=0b 

The LPC clocks can be enabled or disabled by setting or clearing, respectively, the 
LPCC.LPCCLK[1:0]EN bits.

The Clock Run protocol is disabled by default and should only be enabled during 
operating system run-time, once all LPC devices have been initialized. The Clock Run 
protocol is enabled by setting the LPCC.CLKRUN_EN register bit.

Serialized IRQ support may be disabled by setting the OIC.SIRQEN bit to 0b.