Infineon 1024MB, 800MHz, DDR II, PC6400, CL6 HYS64T128000EU-2.5C2 Manuel D’Utilisation
Codes de produits
HYS64T128000EU-2.5C2
HYS[64/72]T512020EU–[25F/2.5/3S]–A
Unbuffered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.0, 2008-06
24
06112008-YHWK-B105
3.6
I
DD
Specifications and Conditions
List of tables defining
I
DD
Specifications and Conditions.
TABLE 16
I
DD
Measurement Conditions
Parameter
Symbol Note
1)2)
3)4)5)
Operating Current 0
One bank Active - Precharge;
One bank Active - Precharge;
t
CK
=
t
CK.MIN
,
t
RC
=
t
RC.MIN
,
t
RAS
=
t
RAS.MIN
, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
I
DD0
Operating Current 1
One bank Active - Read - Precharge;
One bank Active - Read - Precharge;
I
OUT
= 0 mA, BL = 4,
t
CK
=
t
CK.MIN
,
t
RC
=
t
RC.MIN
,
t
RAS
=
t
RAS.MIN
,
t
RCD
=
t
RCD.MIN
, AL = 0, CL = CL
MIN
; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
I
DD1
6)
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK.MIN
; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
I
DD2N
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
I
DD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK.MIN
; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
I
DD2Q
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX
,
t
RP
=
t
RP.MIN
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
OUT
= 0 mA.
I
DD3N
Active Power-Down Current
All banks open;
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
I
DD3P(0)
Active Power-Down Current
All banks open;
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
I
DD3P(1)
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CKMIN
;
t
RAS
=
t
RASMAX
;
t
RP
=
t
RPMIN
; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING;
I
OUT
= 0mA.
I
DD4R
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX.
,
t
RP
=
t
RP.MAX
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
DD4W
Burst Refresh Current
t
CK
=
t
CK.MIN
., Refresh command every
t
RFC
=
t
RFC.MIN
interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD5B
Distributed Refresh Current
t
CK
=
t
CK.MIN.
, Refresh command every
t
RFC
=
t
REFI
interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD5D