Viking Technology Technology Computer Drive PSF1XXXXGXXXX Manuel D’Utilisation
Manual
1/2/2014
PSFS1XXXXGXXXX
Viking Technology
Revision B7
Page 24 of 60
www.vikingtechnology.com
code. Any image not corroborated by at least one other image is discarded. In
this way a reliable firmware image is always chosen on boot-up for execution.
If a firmware image is discarded, a new redundant image is created from the
good images to ensure original levels of protection.
Firmware images are also protected in Flash memory and during fetch by the
maximum ECC correction power, and by RAISE
this way a reliable firmware image is always chosen on boot-up for execution.
If a firmware image is discarded, a new redundant image is created from the
good images to ensure original levels of protection.
Firmware images are also protected in Flash memory and during fetch by the
maximum ECC correction power, and by RAISE
TM
correction technology.
2.6.2 Intelligent Read Disturb Management
Flash memory is primarily at risk from writes and erasures. However, reads also
affect data longevity. Excessive reads of Flash memory cells induce inter-cell
voltage shift, although the effect not as accelerated as write-induced cell
damage. The degradation occurs in data stored in nearby cells, rather than in the
cell being read. Read-induced data degradation is called “Read Disturb.”
The controller provides read operation management to overcome Flash Memory
“Read Disturb” concerns by ensuring that data integrity is not impacted by
multiple reads of the same Flash Memory address. It tracks reads and
automatically and seamlessly recovers and refreshes data in proximity before
that data is negatively impacted. Its superior throughput and latency
performance, delivered over the life of the drive, is not diminished by this process
and the expected data retention capability is assured throughout the warranted
life of the SSD.
affect data longevity. Excessive reads of Flash memory cells induce inter-cell
voltage shift, although the effect not as accelerated as write-induced cell
damage. The degradation occurs in data stored in nearby cells, rather than in the
cell being read. Read-induced data degradation is called “Read Disturb.”
The controller provides read operation management to overcome Flash Memory
“Read Disturb” concerns by ensuring that data integrity is not impacted by
multiple reads of the same Flash Memory address. It tracks reads and
automatically and seamlessly recovers and refreshes data in proximity before
that data is negatively impacted. Its superior throughput and latency
performance, delivered over the life of the drive, is not diminished by this process
and the expected data retention capability is assured throughout the warranted
life of the SSD.
2.6.3 Intelligent Write Operation Management
The controller makes data location/relocation decisions which greatly increase
the life of the SSD.
the life of the SSD.
2.6.3.1 Sophisticated Wear-Leveling
Wear leveling refers to the practice of equalizing the impact of write and erase
operations over the larger pool of Flash memory blocks. Industry-standard wear
leveling techniques focus on conventional schemes that attempt to equalize
writes and erases across blocks. While on the surface this appears to be a
reasonable approach, it is clear that it assumes all blocks will “wear” equally
when written or erased. This is far from the truth. The NAND processor takes
much more into account. It measures a variety of parameters to determine the
actual wear of blocks during P-E cycles, to determine which blocks are impacted
more by erasures and writes over time. That is, it determines actual cell wear, not
simply assumed wear normalized to write/erase events. The controller employs
this information in its superior wear-leveling algorithm along with its ongoing
record of writes and erasures, to ensure each block is impacted by P-E cycles no
operations over the larger pool of Flash memory blocks. Industry-standard wear
leveling techniques focus on conventional schemes that attempt to equalize
writes and erases across blocks. While on the surface this appears to be a
reasonable approach, it is clear that it assumes all blocks will “wear” equally
when written or erased. This is far from the truth. The NAND processor takes
much more into account. It measures a variety of parameters to determine the
actual wear of blocks during P-E cycles, to determine which blocks are impacted
more by erasures and writes over time. That is, it determines actual cell wear, not
simply assumed wear normalized to write/erase events. The controller employs
this information in its superior wear-leveling algorithm along with its ongoing
record of writes and erasures, to ensure each block is impacted by P-E cycles no