Elixir DDR2 2GB, RAM, SO-DIMM, 667MHz M2N2G64TU8HD5B-3C Manuel D’Utilisation
Codes de produits
M2N2G64TU8HD5B-3C
M2N1G64TUH8D4F / M2N2G64TU8HD4B / M2N1G64TUH8D5F / M2N2G64TU8HD5B
M2N1G64TUH8D6F / M2N2G64TU8HD6B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SO-DIMM
REV 1.1
7
07/2008
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Serial Presence Detect
(1GB
– 2 Ranks, 64Mx16 DDR2 SDRAMs)
(Part 1 of 2)
Byte
Description
SPD Entry Value
Serial PD Data Entry (Hex.)
Note
-3C
-AC
-3C
-AC
0
Number of Serial PD Bytes Written during Production
128
80
80
1
Total Number of Bytes in Serial PD device
256
08
08
2
Fundamental Memory Type
DDR2 SDRAM
08
08
3
Number of Row Addresses on Assembly
13
0D
0D
4
Number of Column Addresses on Assembly
10
0A
0A
5
Number of DIMM Ranks, Package, and Height
Module Height = 30.0mm, 2 ranks
61
61
6
Data Width of Assembly
X64
40
40
7
Reserved
Undefined
00
00
8
Voltage Interface Level of this Assembly
SSTL 1.8V
05
05
9
DDR2 SDRAM Device Cycle Time at CL=5
3ns
2.5ns
30
25
10
DDR2 SDRAM Device Access Time (t
ac
) from Clock
at CL=5
0.45ns
0.4ns
45
40
11
DIMM Configuration Type
Non Address/Command Parity,
Non Data ECC,
Non Data Parity,
00
00
12
Refresh Rate/Type
7.8 μs
82
82
13
Primary DDR2 SDRAM Width
X16
10
10
14
Error Checking DDR2 SDRAM Device Width
Undefined
00
00
15
Reserved
Undefined
00
00
16
DDR2 SDRAM Device Attributes: Burst Length
Supported
Supported
4,8
0C
0C
17
DDR2 SDRAM Device Attributes: Number of Device
Banks
Banks
8
08
08
18
DDR2 SDRAM Device Attributes:
Latencies
Supported
3,4,5
38
38
19
DIMM Mechanical Characteristics
x ≤ 3.80 (mm)
01
01
20
DDR2 SDRAM DIMM Type Information
SO-DIMM (67.6mm)
04
04
21
DDR2 SDRAM Module Attributes
Analysis probe installed : No,
FET Switch External Enable : No,
Number of PLLs : 0,
Number of Active Registers : 1,
00
00
22
DDR2 SDRAM Device Attributes: General
Supports Weak Driver,
Supports 50 ohm ODT,
Supports PASR,
07
07
23
Minimum Clock Cycle at CL=4
3.75ns
3D
3D
24
Maximum Data Access Time from Clock at CL=4
0.5ns
50
50
25
Minimum Clock Cycle Time at CL=3
5ns
50
50
26
Maximum Data Access Time from Clock at CL=3
0.6ns
60
60
27
Minimum Row Precharge Time (t
RP
)
15ns
12.5ns
3C
32
28
Minimum Row Active to Row Active delay (t
RRD
)
10ns
28
28
29
Minimum
to delay (t
RCD
)
15ns
12.5ns
3C
32
30
Minimum Active to Precharge Time (t
RAS
)
45ns
2D
2D
31
Module Rank Density
512MB
80
80
32
Address and Command Setup Time Before Clock
(t
(t
IS
)
0.2ns
0.17ns
20
17
33
Address and Command Hold Time After Clock (t
IH
)
0.27ns
0.25ns
27
25
34
Data Input Setup Time Before Clock (t
DS
)
0.1ns
0.05ns
10
05
35
Data Input Hold Time After Clock (tDH)
0.17ns
0.12ns
17
12
36
Write Recovery Time (t
WR
)
15ns
3C
3C